Power-Optimal Ordering of Signals in Parallel Wire Bundles

A computationally efficient technique for reducing interconnect active power is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that crosscapacitances are optimally shared. The existence of a unique power-optimal wire order within a bundle is proven, and a closed form of this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence it can be performed prior to spacing optimization, without affecting the optimality of the combined solution. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from high-end microprocessor circuits in 65nm technology. Interconnect power reduction up to 37% has been observed in such bundles.